FPGA Based Design for Efficient Functioning of Fully Automatic Washing Machine

The design and implementation of an automatic washing machine controller featuring 14 distinct modes is developed using Verilog and deployed on a Field-Programmable Gate Array (FPGA). The system leverages a Finite State Machine (FSM) to control essential operations such as washing, rinsing, and spinning, with automatic mode transitions governed by timing inputs. Simulation and synthesis results confirm the FSM’s correct operation, highlighting smooth mode transitions, efficient resource utilization, and stable timing across all washing modes. The architecture of the washing machine controller is described in detail, including the Verilog-based design, synthesis process, and FPGA deployment. Furthermore, layout design and simulations are discussed, offering insights into the system’s reliability and performance. This implementation provides a scalable and cost-effective solution for modern automatic washing machine control systems.