Ultra CSP/sup TM/: a wafer level package

There has been a significant amount of work over the past 5 years on chip scale packaging. The majority of this work has been an extension of conventional IC packaging technology. Handling discrete devices during IC packaging for this type of CSPs results in a relatively high cost for these packages. This paper presents a wafer scale packaging technology called the Ultra CSP. Advantages of this wafer scale package include commonality with standard IC processing technology for the majority of the packaging process. This paper covers in detail the reliability results achieved for the Ultra CSP for a variety of package sizes and I/O counts covering the range typically seen in microcontrollers, flash and new DRAM architectures. There is also significant discussion on optimization work on board pad size, solder paste volume and solder paste type.