A Sub-100 nW Power-on-Reset Circuit with Integrated Brown-Out Detection and Autonomous Power Gating for Edge Devices

This paper presents a compact power-on reset (POR) circuit with integrated brown-out reset (BOR) functionality and autonomous power gating. The proposed POR circuit employs a voltage gap generator to provide a reference for the POR threshold, enabling rapid and programmable POR operation over a wide range of supply ramping time$(t_{\text{ramp }})$. Additionally, the proposed POR circuit incorporates a power gating controller to reduce quiescent current, which also monitors supply voltage (VDD) droop and automatically reactivates the circuit to generate the BOR signal. Implemented in a$\mathbf{2 8}-\mathbf{n m}$CMOS process, the prototype POR circuit supports a configurable POR level above 700 mV at a$0.8-1.2-\mathrm{V} V_{D D}$and guarantees a maximum POR delay of$16.4 \mu \mathrm{s}$over a broad range of$t_{\text{ramp }}$from$1 \mu \mathrm{s}$to 1 s. Owing to the autonomous power gating, the prototype consumes a quiescent current of 95 nA at a$1-V V_{D D}$and occupies an active area of$580 \mu \mathrm{m}^{2}$.