US-BIP: A Unified and Saturation-Aware Processor for Efficient Binary Neural Network Inference

US-BIP, a resource-efficient processor for binary neural networks inference is presented. US-BIP incorporates a single compute unit designed based on a unified architecture that can support all block types with minimal overhead. The compute unit processes every block at full utilization, leading to high resource efficiency. Furthermore, the partial-sum compute logic is designed by employing saturating arithmetic, with the bit-width optimized based on saturation-aware training. US-BIP, implemented on a 28nm FPGA using 3.59k LUTs, achieves a resource efficiency of 20.86MOP/s/LUT and an inference accuracy of 88.47% on the CIFAR-10 classification task.