Characterization of plasma-induced damage on TiN/HfO 2 /SiO 2 stacked structure during multi-Vt process for advanced CMOS using different dry etching gas chemistry

Abstract To investigate the effects of the process for realizing multi-Vt solution in the advanced logic field effect transistors (FETs), plasma-induced damage (PID) on TiN/HfO 2 /SiO 2 stacked gate structure is examined using different plasma source gas chemistries, i.e., H-based plasma or O-based plasma. It was observed that PID including an increase in HfO 2 wet etch rate, oxide interfacial layer regrowth, and interface charge traps became more significant with H-based plasma process than with O-based plasma process. We found that lowering process pressure down to sub-Pa, while maintaining high-density plasma using microwave electron cyclotron resonance (M-ECR) plasma is effective for H-based plasma process to suppress PID.