锁相环
抖动
带宽(计算)
电子工程
计算机科学
相位噪声
CMOS芯片
传递函数
PLL多位
数字控制
带宽扩展
控制理论(社会学)
工程类
电气工程
数字信号处理
控制(管理)
电信
人工智能
音频信号
作者
Mario Mercandelli,Luigi M. E. Grimaldi,Luca Bertulessi,Carlo Samori,A.L. Lacaita,Salvatore Levantino
出处
期刊:IEEE Journal of Solid-state Circuits
[Institute of Electrical and Electronics Engineers]
日期:2018-11-01
卷期号:53 (11): 3243-3255
被引量:14
标识
DOI:10.1109/jssc.2018.2866454
摘要
This paper presents a technique to regulate the bandwidth of digital phase-locked loops (PLLs), where a fully digital automatic control circuit, running in background, is used to desensitize loop gain from analog parameters. The method that is based on an adaptive least-mean-squares algorithm requires no injection of a training sequence, potentially degrading phase noise performance, and is suitable in particular for bang-bang PLLs, where the bandwidth depends on the input noise. The operating principle is first introduced and discussed with the help of an intuitive time-domain model, and the algorithm extension addressing the practical implementation issues associated with loop latency is then presented. The calibration circuit is embedded in a 65-nm CMOS digital PLL that achieves 400-fs integrated rms jitter with a power consumption of 4.5 mW. The algorithm enables digital programmability of loop bandwidth from 100 kHz to 2 MHz with an error below 1 dB between the theoretical and measured PLL noise transfer functions.
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