Degradation of VDMOS Under Simultaneous and Sequential Stress of Gamma Ray Irradiation and Annealing Process

In this article, the degradation mechanisms of radiation-hardened vertical double-diffused MOSFETs (VD-MOSFET) experiencing gamma ray irradiation and annealing sequentially experiment device and simultaneously experiment device (Si-ED) are studied and compared. Experiments demonstrate that the Si-ED irradiated with gate bias (+12 V) has a lower oxide-trapped charges increment ( $\Delta {N}_{\text {ot}})$ and higher interface states increment ( $\Delta {N}_{\text {it}})$ , compared to those of sequential experiment device (Se-ED). However, for Si-ED irradiated with drain bias (200 V), it shows lower $\Delta {N}_{\text {ot}}$ and $\Delta {N}_{\text {it}}$ than those of Se-EDs, which is similar to that observed in the case of devices irradiated with three-terminal bias (200-V drain bias, −10-V gate bias, and source grounded). In addition, for all cases, it is seen that the drain-biased devices own a larger $\Delta {N}_{\text {ot}}$ but a smaller $\Delta {N}_{\text {it}}$ , compared to those of gate-biased ones, and the three-terminal-biased devices show the lowest, especially in Si-ED. As a result, the variations of $\Delta {N}_{\text {ot}}$ and $\Delta {N}_{\text {it}}$ could cause different degradations of threshold voltage, breakdown voltage, leakage current, and ON-state resistance of devices, which would inevitably threaten the proper functioning of electrical systems. Moreover, in this article, it is concluded that the existing standard, i.e., accelerated annealing after irradiation, cannot reflect the actual radiation reliability of devices. Other evaluation methods regarding total ionizing dose (TID) need to be further explored comprehensively.