50 nm DrGaN in 3D monolithic GaN MOSHEMT and Silicon PMOS process on 300 mm GaN-on-Si(111)

• Industry's first short-channel 50 nm “DrGaN” is fabricated in 300 mm GaN-on-silicon process. • Enhancement-mode high-k GaN MOSHEMT transistors are demonstrated with integrated Si PMOS transistors. • A gate-last 3D monolithic integration process flow by 3D monolithic layer transfer is demonstrated. • The “DrGaN” features CMOS driver integration with GaN power switch, exhibiting R ON of 0.56 m Ω -mm 2 and leakage below 0.1 mA (switch transistor width of 470.59 mm). We demonstrate a 50 nm DrGaN technology fabricated in a 300 mm GaN-on-Silicon process combining E-mode high-k dielectric GaN MOSHEMT with integrated 3D monolithic Si PMOS by layer transfer. The DrGaN consists of a channel-length 50 nm GaN MOSHEMT power transistor with figure-of-merit (FOM) of 1.1 (m Ω -nC) -1 and total width of 470.59 mm, integrated with a CMOS gate driver comprising a 27.19 mm wide 180 nm Si PMOS and 49.54 mm wide 130 nm GaN NMOS. In this work, we employed a gate-last 3D monolithic integration process, where the high temperature activation steps for the Si PMOS transistors are completed before the gate dielectric of the GaN MOSHEMT transistors is deposited.