A Method of High-speed Parallel CRC Computation

This paper presents a new parallel CRC (Cyclic Redundancy Check) computation method (named PQC-CRC) for high-speed communication. As the communication bandwidth increases, the number of bits to be processed in parallel, i.e. the parallel width, for CRC computation is also getting bigger and bigger. So the length of the message being sent is possibly no longer an integer multiple of the parallel width, and invalid bytes may occur in the last cycle. Multi-path selection method is usually be used to handle the problem, which greatly increases the resource consumption as the parallel width increases. The PQC-CRC method first appends the message bit sequence with zeros to make its length an integer multiple of the parallel width. Then, it performs CRC computation, where the data widths in each cycle are the same. During the last cycle calculation, not only the remainder is saved but also the partial quotient obtained from that cycle is kept. Finally, depending on the number of invalid bits, the partial quotient is multiplied by the generating polynomial and added to the remainder saved in the last cycle to obtain the final correct result. The experimental results show that the PQC-CRC method effectively reduces the logical resources consumed and also increases the maximum clock frequency when compared with the multi-path selection method.