Comprehensive PDN/PSIJ analysis of silicon capacitor use for 8.533 GT/s LPDDR5X application

Silicon capacitors have large capacitance values in small areas. When mounted as discrete capacitors on an IC package, these capacitors create a high-capacitance, low-inductance branch in the power distribution network (PDN). This branch can effectively service the high-frequency needs of an IO switching load, reducing PDN noise and jitter. In this paper, we methodically study silicon-capacitor technology options in terms of capacitance values/size and their effectiveness in controlling PDN noise and power supply induced jitter (PSIJ) for an IO supply in an LPDDR5X application. This technology is especially useful for a system on chip (SoC) with many IO rails such as DDR and SerDes since the routing at the perimeter of the SoC package and real estate of the package footprint are extremely limited. A custom test board for characterization of silicon capacitors has been designed and fabricated carefully. Measurement was done using a high-frequency vector network analyzer (VNA). The result shows the measured capacitance value agrees well with the fabricator's expectations and capacitor model, and that equivalent series inductance (ESL) in a silicon capacitor is less sensitive to frequency than inductance in a conventional multilayer ceramic capacitor (MLCC). The correlated silicon capacitor model has been used for frequency-domain PDN simulation and time-domain PSIJ simulations. The simulations found that adding silicon capacitors as land-side capacitors (LSCs) lowered the impedance of the PDN at frequencies usually served by on-board MLCCs. This finding suggests that the use of silicon capacitors can lead to fewer MLCCs on boards. Moreover, the effectiveness of silicon capacitors in controlling PSIJ can be seen with simulations that plot voltage noise or PSIJ with respect to capacitance value. Since silicon capacitors have very high capacitance density, it can be found that even a small silicon capacitor can provide enough charge to control the sharpest droops in an IO PDN of an LPDDR5X application, which can be applicable to other interfaces such as SerDes and RF.