Design techniques for reference clock jitter optimization for high speed PHYs

This paper presents full chip and power delivery design guidelines for optimal current mode logic (CML) based reference clock distribution for high speed IPs like PCIE gen5 and Ethernet 25Gbps+/PAM-4 which have extremely tight jitter requirements. We have presented design optimization techniques for die routes with respect to their jitter performance as well as provided guidelines on optimal CML buffer placements in order to hit Ethernet 156.25 Mhz reference clock jitter specs as per the 802.3 IEEE standard. We also highlight the techniques we have employed to reduce noise on the supplies. We could reduce the AC peak to peak noise on the supplies by 50% using our methods. We believe our methods will be very useful for high speed serializer deserializer designs in deep submicron technologies at very high data rates.