A 160-Gb/s 0.37-pJ/bit PAM4 Optical Receiver in 28-nm CMOS

This paper presents a 160-Gb/s PAM4 optical receiver implemented in 28-nm CMOS process. The receiver consists of an equalized inverter-based transimpedance amplifier (TIA), a proposed 2-stage cascode-based single-to-differential converter (S2D), and a 2-stage variable gain amplifier (VGA). Inductive peaking techniques are adopted in equalized TIA and S2D for broadening bandwidth. Consuming 58.79-mW power, the proposed receiver achieves a differential conversion gain of 76.1 dBΩ with 0.2-dB and 3.2° imbalances in amplitude and phase, respectively.