Influence of Substrate and EPI Buffer on SiC Bipolar Degradation for Different Voltage Classes at High Current Levels

In this study, we investigate the critical impact of the substrate quality and epi-buffer design on bipolar degradation in SiC MOSFETs at very high current levels. The test procedure and test results, including a defect analysis, are presented in this paper. Our findings demonstrate that a safe operating area can be defined for each substrate vendor and epi design, up to a specific current density.