Stable Analog Weight Programming in Single‐Crystalline van der Waals Ferroelectric Transistors for Reliable Computing‐in‐Memory

ABSTRACT Emerging ferroelectric non‐volatile memories are revolutionizing von Neumann architectures by providing efficient hardware for both AI training and inference. However, as ferroelectric dimensions scale toward the nanoscale, reliable modulation is hindered by interfacial degradation and phase instability, leading to synaptic weight drift and computational inaccuracies. Here, a high‐performance ferroelectric‐van der Waals transistor (FeFET) for computing‐in‐memory by integrating a single‐crystalline Bi 2 O 2 Se (BOS) layer into a ferroelectric/MoS 2 heterostructure is demonstrated. The implementation of an asymmetrical capacitive stack ensures effective polarization‐charge compensation during fine‐state switching, achieving precise multi‐level weight programming with significantly suppressed carrier fluctuations. Fabricated through a low‐temperature process, the BOS‐based FeFET exhibits exceptional reliability, including 10‐year retention at 85°C, endurance exceeding 10 11 cycles, stable 32‐state analog switching with 0.9% retention variation over 10 000 s, and ultra‐low programming error. Atomically smooth heterointerfaces yield high spatial uniformity (7% variation) across the FeFET array, enabling a hardware neural network that achieves 98.5% accuracy in nonlinear classification. Furthermore, by incorporating intrinsic ferroelectric switching variance into the training phase, it is elucidated how device imperfections can be leveraged to reshape learning dynamics in pixel‐wise semantic segmentation. This work establishes a comprehensive co‐design methodology bridging advanced ferroelectric materials, device engineering, and algorithmic optimization for next‐generation neuromorphic computing.