A Process-Robust Split-Gate eFlash Memory with Spacer-Defined Floating Gate in 55-nm Node

To overcome the critical performance-manufacturability-cost trade-off in Internet of Things (IoT) and edge devices, this paper presents a split-gate embedded Flash (eFlash) memory in a 55-nm technology node. The memory utilizes a spacer-defined floating gate (FG) to co-optimize high performance, high manufacturability, and low cost. The proposed cell achieves a low read voltage of 1.5 V, program/erase operations at ±7 V, and a fast program time of 1 μs, enabling high energy efficiency at both the cell and system levels. The self-aligned FG structure inherently eliminates etchinduced variations, demonstrating enhanced process robustness that is confirmed by a high yield in fully functional array testing. This work provides a highly competitive solution for balancing performance, manufacturability, and cost in advanced-node embedded Flash memories.