CMOS芯片
电子工程
电气工程
计算机科学
收发机
低压
发射机
相位噪声
锁相环
物理
带宽(计算)
作者
Tero Nieminen,Tero Tikka,Yury Antonov,Olli Viitala,Kari Stadius,Martti Voutilainen,Jussi Ryynanen
标识
DOI:10.1007/s10470-014-0433-7
摘要
A scalable low-voltage signaling (SLVS) serial link transmitter for MIPI M-PHY is presented in this paper. It delivers 200---400 mV pp signals at date rates of 1.25---5.8 Gbps. The integrated circuit entity consists of the actual SLVS driver, an ADPLL-based clock synthesizer with a frequency multiplier, and an internal test signal generator with pseudo-random binary sequences. The circuit has been fabricated in a 40-nm CMOS process. The overall active die area is 0.2 mm2, while the actual driver occupies only 190 μm2. In this work it was confirmed that a low-power SLVS driver meets the stringent common-mode noise generation limits set for serial interfaces used in mobile devices. Noise power density remains below ?138 dBm/Hz at all data rates. Total power consumption of the transmitter is kept low by utilizing dynamic CMOS pre-drivers and a low drop-out voltage regulator. It achieves power efficiency of 0.44---1.4 mW/Gbps with external clock and 2.6---4.7 mW/Gbps with clock synthesizer.
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