Image-based overlay mark shrinkage study for advanced technology node

As design rules continue to shrink down, IC industry have to face two big challenges: high cost and marginal process tolerance. For overlay metrology, since double patterning techniques have been applied in patterning processes normally, total layers of overlay measurement would be increased to 3x that of single patterning processes. That means more areas in the wafer should be remained for the placement of overlay marks in the scribe lines, which would be disliked by IC industry. Plus, overlay margins of device become tighter, and it requires overlay tools to control the measurement accuracy and precision to higher levels. According to ITRS Roadmap of 2012, the 20 nm and beyond nodes require 4 nm overlay for critical layers [1]. In this paper, we compare IBO marks (standard box in box, bar in bar and AIM) with different target sizes and target segmentations in real products. The overlay response and fingerprint of these targets are compared. We designed CMP (Chemical Mechanic Polish) split experiments for exploring targets sensitive to process variations. The result of our study will be presented and discussed.