A novel design of full adder cell for VLSI applications

The state-of-the-art digital integrated circuits (ICs) are becoming increasingly complex due to the increasing functionality along with high-performance and ultra-low power dissipation requirement. To meet the aforementioned requirement, a new low power and high performance 1-bit full adder cell is implemented based on gate diffusion input (GDI) and pass transistor logic (PTL) techniques. The delay, power, power delay product (PDP) and energy-delay product (EDP) are extracted and compared for the proposed full adder cell with other seven widely used full adders. The area is compared at 0.18 µm and 0.090 µm CMOS technology. The average power dissipation of proposed adder is 1.063 µW, C-CMOS is next higher value of 1.377 µW and the NMNFA exhibits a highest value of 3.217 µW at a supply voltage of 1.2 V. The proposed adder reveals lower PDP (0.265 fJ) than the other adders. At all supply voltages, the proposed adder delivers low EDP value (0.070 fJ*nS) and it is minimum at 1.8 V because the delay is low at the same point which is dominating parameter in EDP. At a supply voltage of 1.2 V, the proposed adder exhibits improved performance EDP of 69.07% over the other best reported minority-function bridge-style full adder in this paper.