Self-assembly technology for reconfigured wafer-to-wafer 3D integration

We have introduced a new 3D stacking technology called reconfigured wafer-to-wafer 3D integration using surface tension-powered multichip self-assembly and multichip transfer techniques. Many Si chips were simultaneously self-assembled to a carrier wafer named “reconfigured wafer”. High-precision chip alignment with sub-micron-scale accuracy can be realized by optimizing self-assembly conditions. In addition, we developed a new self-assembled multichip bonder to three-dimensionally stack many known good dies (KDGs) on 8-inch wafers at the wafer level. By using the equipment, the many self-assembled Si chips were transferred to another target wafer in batch.