DFM methodology for automatic layout hot spot removal

As technology migrates from 90nm to 65nm and 45nm, it is increasingly difficult to achieve fast yield ramp due to random defects, process variations, systematic yield problems and other limitations referred to as design-for-manufacturing (DFM) issues. At 90nm and finer process nodes, these problems often appear as layout hot spots. To avoid downstream yield and manufacturing problems relating to layout hot spots, it is imperative that the layout of library cells used in system-on-chip (SOC) designs are printable, OPC compliant, litho compliant, as insensitive as possible to process variations, and capable of achieving the high yield. It is not uncommon to have fifty thousand plus hot spots in a typical 65nm SOC device1. This paper describes a DFM methodology and a system for improving the quality of cell layouts, using physical layout optimization. This system takes into account actual foundry information, including defect data, fab-specific optical and litho settings, simple design rules and composite design rules. The automated layout optimization system analyzes a GDSII layout, determines the potential impact of failure and eliminates hot spots using 2-D physical layout optimization, resulting in an enhanced GDSII layout that is correct by construction and optimized for yield.