Characteristics and mechanisms of subthreshold voltage hysteresis in 4H-SiC MOSFETs*

In order to investigate the characteristics and mechanisms of subthreshold voltage hysteresis (Δ V th,sub ) of 4H-SiC metal–oxide–semiconductor field-effect transistors (MOSFETs), 4H-SiC planar and trench MOSFETs and corresponding P-type planar and trench metal–oxide-semiconductor (MOS) capacitors are fabricated and characterized. Compared with planar MOSFEF, the trench MOSFET shows hardly larger Δ V th,sub in wide temperature range from 25 °C to 300 °C. When operating temperature range is from 25 °C to 300 °C, the off-state negative V gs of planar and trench MOSFETs should be safely above –4 V and –2 V, respectively, to alleviate the effect of Δ V th,sub on the normal operation. With the help of P-type planar and trench MOS capacitors, it is confirmed that the obvious Δ V th,sub of 4H-SiC MOSFET originates from the high density of the hole interface traps between intrinsic Fermi energy level ( E i ) and valence band ( E v ). The maximum Δ V th,sub of trench MOSFET is about twelve times larger than that of planar MOSFET, owing to higher density of interface states ( D it ) between E i and E v . These research results will be very helpful for the application of 4H-SiC MOSFET and the improvement of Δ V th,sub of 4H-SiC MOSFET, especially in 4H-SiC trench MOSFET.