A BRIEF REVIEW OF SOURCE/DRAIN ENGINEERING IN CMOS TECHNOLOGY AND FUTURE OUTLOOK

Source/Drain stressor engineering has been one of the key factors for aggressively scaled devices. Epitaxial SiGe and SiC(P) are used for the stressor materials in pMOSFET and nMOSFET respectively. In this paper, we summarized the process evolutions in the field of source/drain engineering since 28 nm planar device structures until the most recent FinFET technology with smaller dimensions. Key process parameters and how they affect device performances are discussed in details. Also, we provided an outlook of the future applications of epitaxial processes in CMOS technology with smaller dimensions.