德拉姆
与非门
电气工程
材料科学
晶体管
光电子学
缩放比例
电容器
延迟时间
计算机科学
逻辑门
计算机硬件
电压
工程类
半导体存储器
内存控制器
数学
几何学
作者
Wei‐Chen Chen,Hang-Ting Lue,Tzu-Hsuan Hsu,Keh-Chung Wang,Chih‐Yuan Lu
标识
DOI:10.1109/imw56887.2023.10145823
摘要
Planar 1T1C DRAM has encountered numerous challenges as it reaches beyond $1 \mathrm{z}-\mathrm{nm}$ node. The daunting task of manufacturing a low-leakage access transistor and high aspectratio capacitor necessitates a disruptive technology to continue the relentless scaling path similar to the migration of $2 D$ to $3 D$ NAND. In this work, we will touch up on the scaling difficulties associated with 2D 1T1C DRAM and then examine the possible options of 3D DRAM, including flipped 1T1C DRAM, 2T0C gain-cell DRAM, and 3D stackable gate-controlled-thyristor (GCT) DRAM. We will show that the capacitor-less GCT DRAM, which shares the architectural features of CMOS nanosheet and 3D NAND, possesses good potential of realizing a truly 3D stackable structure. Furthermore, the scaling capability toward $10 \mathrm{~nm}$ of such GCT device is verified by TCAD simulation when the channel length and width are downscaled simultaneously. Meanwhile, the gate oxide thickness thinning is unnecessary because the thyristor operation principles are different from the MOSFET. The simulated $\mathrm{Lch} / \mathrm{Wch}=10 \mathrm{~nm}$ GCT device can well preserve $\gt 2 \mathrm{~V}$ hysteresis memory window, large read current ON/OFF ratio of $\gt 1 E 8$, and $110 \mu \mathrm{A}$ sensing current window, paving a way for aggressive $X / Y$ pitch scaling for the $3 D$ stackable DRAM device.
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