Design of a Hysteresis Comparator

Comparator is widely used in conversion of analog signal to digital signal. In analog-to-digital conversion, the input signal is sampled by comparator to determined the output digital signal. Hysteresis comparator also called sluggish comparator with superior anti noise ability plays an important role in comparator. The paper describes a hysteresis comparator with simple structure and hysteresis voltage threshold design flexibility. At the same time PMOS are the differential input transistors and the comparator has high common mode input range and large slew rate. The design with turning point of voltage difference 200 m V is simulated with 0.18 μm CMOS process and the results are accord with the desired outcome.