Reliability and Performance Improvements of 3D System-in-Packages in Fan-Out Wafer Level Packaging

Recent development efforts for fan-out wafer level packaging (FO-WLP) have focused on system-in-package (SiP) solutions using both 2D and 3D packaging structures. Creating connections between the various elements of the system is one of the critical requirements of the packaging technology. The connections must provide a low loss pathway, exhibit manufacturability and prove reliable. Effective system connections enable complex yet volumetrically and electrically efficient systems to be constructed. The combination of various system elements including, but not limited to, SMDs, CMOS, GaAs, MEMS, power devices, imaging sensors or IPDs gives system designers the capability to generate novel systems and differentiating solutions. Both 2D and 3D SiPs based upon the Redistributed Chi Package (RCP) have been developed for consumer, defense and medical applications. In RCP (i.e. FO-WLP), 2D systems are readily achieved through the use of existing packaging processes, materials and structures. For 3D embodiments, the FO-WLP technology must be expanded. 3D integration in FO-WLP can be achieved with the use of package-on-package (PoP), embedded substrates, package edge connections, die stacking or even TSV approaches. However, a more typical solution to the 3D integration challenge is the through package via (TPV). TPVs can resemble substrate vias but their construction is typically different. Regardless of materials selected or processes used to create the TPV, system connections using a TPV will require a certain level of performance and reliability. Reliability and performance improvements to the 3D RCP technology will be presented.