An Analysis of UIS Failure Mechanism of 4H-SiC MOSFET in Transition Region

This study reveals an unreported failure mechanism of 4H-SiC MOSFET during unclamped inductive switching (UIS) testing. The failure occurs in the transition region around the gate pad, which is located at the gate oxide / field oxide interface on the main junction. With the increase of UIS energy, the static characteristics of the device are characterized by progressive degradation. Failure analysis indicates a progressive damage process in the gate oxide layer above the main junction in the transition region, consistent with the static characteristic changes. Combined with the layout structure and simulation verification, the failure is due to the local electro-thermal stress caused by the avalanche current concentration effect and the blocking of the hole current conduction in the main junction. At the same time, the mismatch of the thermal expansion coefficient (CTE) between $\mathbf{4 H - S i C} / \text{SiO}_{2} /$ polysilicon aggravates the thermal mechanical stress. Based on this, a layout optimization scheme is proposed to enhance the UIS robustness of $4 \mathrm{H}-\text{SiC}$ MOSFET by introducing source contacts in the transition region to export the hole current.