Detecting Asymmetries Within Multi-Chip SiC Power Modules by Means of the Kelvin Source

With their increasing power level, Silicon-Carbide (SiC) devices are more and more realized as multi-chip modules. Due to the faster switching behavior of these devices, the current sharing among parallel chips gets more challenging. Current asymmetries of parallel chips can be caused by variations in chip-level parameters, by the module interconnection design or by all kinds of degradation mechanisms. If asymmetries within the module lead to unbalanced current distributions, the safe operating area (SOA) and the reliability can be affected. This paper aims to experimentally detect and characterize asymmetric current distributions by means of the chips’ common Kelvin-source path. As a potential use-case, an asymmetric current distribution was deliberately induced by removing source bond wires of parallel connected SiC-MOSFET chips, resembling a bond wire lift-off due to fatigue.