CMOS芯片
比较器
歪斜
偏移量(计算机科学)
电子工程
计算机科学
时钟频率
晶体管
绝缘体上的硅
电气工程
工程类
物理
光电子学
电压
电信
硅
程序设计语言
作者
Vanessa Hung-Chu Chen,Lawrence T. Pileggi
出处
期刊:IEEE Journal of Solid-state Circuits
[Institute of Electrical and Electronics Engineers]
日期:2014-12-01
卷期号:49 (12): 2891-2901
被引量:46
标识
DOI:10.1109/jssc.2014.2364043
摘要
A 20 GS/s 6b time-interleaved ADC is implemented in 32 nm CMOS SOI with an embedded time-to-digital converter to sense timing skew, and the randomness of process mismatch is exploited to compensate for the clock misalignment and dynamic offset errors of comparators that occur during high-speed operation. To achieve low-power consumption at high-speed operation with small-size transistors, a low-complexity on-chip calibration reduces gain, offset, and delay mismatches in background. With the timing skew calibration, the spurs due to clock misalignment are reduced by 20 dB. The proposed ADC achieves an SNDR of 30.7 dB at Nyquist frequency and consumes only 69.5 mW with a figure-of-merit of 124 J/conv-step.
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