MOTA: Mapping and Optimization of ASIC-Accelerated TFHE Transciphering

Fully Homomorphic Encryption (FHE) enables computation on encrypted data without decryption, preserving data confidentiality. However, encrypting large datasets directly with FHE is often impractical due to substantial ciphertext expansion and communication overhead. Transciphering offers an efficient alternative by encrypting data with a lightweight symmetric cipher (e.g., AES) and then converting it into FHE ciphertext on the server. In this work, we propose MOTA, a framework for mapping and optimization of TFHE-friendly AES transciphering on near-memory FHE accelerators. We construct a compound gate library tailored for AES logic, designed for efficient mapping onto TFHE-compatible hardware implementations. We then optimize the circuit representation through an integer linear programming (ILP) formulation built upon the compound gate library. The resulting circuits are mapped to a representative class of programmable near-memory ASIC accelerators, enabling efficient execution with reduced data movement and specialized TFHE control flow. Experimental results demonstrate that MOTA achieves significant improvements in evaluation latency over conventional TFHE-friendly AES designs.