A complementary lithographic simulation method for improved yields following full-chip DRC

In this paper the impact of photolithography simulations on the workflow for accomplishing Full Chip DRC verification was investigated. The potential for simulation to reliably replace trial and error was determined. Initially simulations were done for a poly-Si layer, using KLA's PROLITH v8 tool, to predict printability of Full Chip DRC. The simulation results were then compared to actual printed features. Photo resist parameter calibration was determined to have significant impact on the accuracy of printed feature predictions. The benefits of using simulations in the DRC verification workflow was determined in terms of cycle time and mask set cost reductions.