10 kV, 250°C Operational, Enhancement-Mode Ga2O3 JFET with Charge-Balance and Hybrid-Drain Designs

We report the first 10 kV Enhancement-mode (E-mode) transistor in ultra-wide bandgap (UWBG) materials. This lateral Ga2O3 junction-gate field-effect-transistor (JFET) deploys a highly-doped p-type NiO for E-mode gate, as well as the lowly-doped NiO superjunction and hybrid-drain structures for electric field management. The Ga2O3 channel is optimized with a $1.5\times 10^{18}\text{cm}^{-3}$ doping and two thickness designs of 50 and 160 nm. At 25°C, both JFETs achieve the E-mode and > 10 kV breakdown voltage $(BV)$, with the specific on-resistance $(R_{\text{ON},\text{SP}})$ being 92 and $703\ \mathrm{m}\Omega\cdot \text{cm}^{2}$ for the thick-and thin-channel designs, respectively. At 250°C, the thin-channel JFET remains E-mode with a $BV$ over 10 kV at zero gate-source bias $(V_{\text{GS}})$. In contrast, the thick-channel JFET turns into depletion-mode (D-mode) at high temperatures $(T)$ and maintains 10 kV $BV$ only up to 150°C, due to the insufficient gate control to counter the drain-induced barrier lowering (DIBL) effect. This implies a trade-off between $R_{\text{ON},\text{SP}}$ and $\text{high}-T$ stability. Both devices survive the $\text{high}-T$ gate bias (HTGB) and 3 kV $\text{high}-T$ reverse bias (HTRB) reliability tests. Overall, our device presents not only the best figure-of-merits (FOMs) in all >3 kV UWBG transistors, but also the first 250°C operation and 3 kV reliability data in all high-voltage transistors beyond Si and SiC. The unveiled device physics and trade-off can also guide the development of future high-voltage, $\text{high}-T$ power transistors.