Thermal Analysis of Dual-sided Cooling for Backside Power Delivery Networks (BSPDN) on 2.5D Glass/Silicon Interposer Package

This study explores advanced cooling strategies for Backside Power Delivery Networks (BSPDN) within a 2.5D interposer-based package integrated with a logic die and High Bandwidth Memory (HBM) modules. Comparative modeling analysis of cooling techniques reveals that utilizing topside direct-on-chip microjet cooling alongside a glass-based interposer package has the potential to decrease HBM temperatures significantly, potentially by a factor of 5. This reduction is achieved by minimizing the thermal coupling between the logic and HBM components. In addition, dual-sided cooling utilizing topside microjet cooling and glass/silicon interposer embedded microchannel cooling is proposed to address the thermal bottleneck of BSPDN configurations owing to the lower thermal conductivity SiO2 bonding layer. The modeling results indicate that the proposed dual-sided cooling approach can decrease the logic maximum temperatures by 22% while simultaneously mitigating the thermal coupling between the logic and HBM components.