电感
引线键合
电源模块
工作台
材料科学
MOSFET
功率(物理)
电子工程
碳化硅
等效串联电感
热阻
结温
电气工程
印刷电路板
计算机科学
拓扑(电路)
热的
机械工程
工程类
电压
晶体管
物理
复合材料
炸薯条
量子力学
气象学
可视化
作者
Laili Wang,Tongyu Zhang,Fengtao Yang,Dingkun Ma,Cheng Zhao,Yunqing Pei,Yongmei Gan
出处
期刊:IEEE Transactions on Power Electronics
[Institute of Electrical and Electronics Engineers]
日期:2022-07-01
卷期号:37 (7): 7952-7964
被引量:14
标识
DOI:10.1109/tpel.2022.3141373
摘要
Cu clip-bonding is a promising packaging method for lower resistance, lower inductance, and higher reliability than wire-bonding. Previous studies only simply replace bond wires with Cu clips on an individual die. However, current sharing and thermal coupling issues among multichip modules are still big challenges in the clip-bonded silicon carbide (SiC) mosfet power module. In this article, a novel source inductance optimization method is proposed. Extra modification paths (MPs) on Cu clips are used in this method. A clip-bonded half-bridge multichip SiC power module is designed and fabricated to verify the superiority of the method. In a simple straight layout, the distance between adjacent dies is large enough to avoid heat concentration and junction temperature differences resulting from the thermal coupling effect. The MPs structure on the Cu clip is designed to optimize the power source inductances. Parasitic circuit model and mathematical analysis are derived to demonstrate the features of proposed MPs. Simulations and experiments workbench are conducted to analyze drain current sharing performance. Derivation and simulation show the highest branch's inductance is reduced. Test results show the current imbalance and loss imbalance are relatively mitigated, which proves that the effect of power inductances imbalance is suppressed by the proposed optimization method.
科研通智能强力驱动
Strongly Powered by AbleSci AI