Novel glitch reduction techniques for ultra-low power digital design

This paper presents some proposed and new techniques in comparison to a traditional one for register-transfer level (RTL) circuits. The traditional technique focuses on killing glitches in both the control and data path parts of the circuit to reduce power consumption. By analyzing and simulating the generation and propagation of glitches in some benchmark circuits, we found out some issues when killing glitches in both control and data paths using traditional approach. In some cases, the traditional approach minimizing glitches, at the same time, still consume a huge amount of power though glitches are killed because a great many extra transistors are brought as a trade-off. And much more extra transistors have a deep impact on area and delay, which is neglected in the traditional technique. Besides, it could not kill glitches in control path when two selected data are not correlated. Therefore, our key point of this paper is to solve these issues that the traditional technique leaves, and propose more techniques to kill glitches in other cases.