A Temporal Partitioning Methodology for Reconfigurable High Performance Computers

This paper presents a Design Space Exploration(DSE) methodology based on a temporal partitioning strategy for mapping of massive computational dataflow problems into FPGAs. In this approach the FPGAs work as co-processors in a hypothetic reconfigurable computing architecture. The temporal partitioning is based on Tabu Search strategies and libraries of IP-cores. This methodology allows Design Space Exploration for optimization of dataflow implementation into the FPGA and pre-runtime analysis. Results of this DSE technique, for synthetic benchmarks, have reached very good performance and sometimes better than others in the literature.