A transient enhanced FVF LDO regulator for 400 pF to 10 nF capacitive loads with improved regulation

A flipped voltage follower (FVF) low dropout (LDO) regulator is proposed in this work for the load capacitor ranges of 400 pF to 10 nF. With load capacitor ranges of 400 pF to 10 nF, the proposed LDO can drive a peak load current of 20 mA while maintaining adequate stability margins. In this work, a simple single transistor discharge circuit is proposed that discharges the large load capacitor during the overshoot transient and reduces the settling time from μs to ns. The enhanced super source follower (ESSF) presented in this work enhances the slew rate at the output of ESSF by providing increased bias current only during the transient and returning to normal after the transient. It also improves the DC gain of the LDO regulator. The proposed LDO uses two separate loops to improve the LDO regulator’s performance. The frequency compensator reported in this paper combines two small compensating capacitors, a variable MOS resistor, and a feed–forward transistor to stabilize the LDO regulator’s main loop. The proposed FVF LDO regulator is designed and realized using 130 nm CMOS technology. The proposed LDO regulator is stable, with a minimum phase margin of 50.4o for a load capacitor ranging from 400 pF to 10 nF and a peak load current of 20 mA. It achieves a settling time of 885 ns, even with the large load capacitor of 10 nF.