Investigating Degradation Behavior of InGaZnO Thin-Film Transistors Induced by Charge-Trapping Effect under DC and AC Gate-Bias Stress

This paper investigates the degradation mechanism of amorphous InGaZnO thin-film transistors under DC and AC gate bias stress. Comparing the degradation behavior at equal accumulated effective stress time, more pronounced threshold voltage shift under AC positive gate bias stress in comparison with DC stress indicates extra electron-trapping phenomenon occurs during the duration of rising/falling time in pulse. Contrarily, illuminated AC negative gate bias stress exhibits much less threshold voltage shift than DC stress, which suggesting the photo-generated hole does not has sufficient time to drift to the interface of IGZO/gate insulator and causes hole-trapping under AC operation. Since the evolution of threshold voltage fits the stretched-exponential equation well, the different degradation tendencies under DC/AC stress can be attributed to the different electron- and hole-trapping efficiencies, and this is further verified by varying pulse waveform.