A Transient-Enhanced Low-Dropout Regulator in 0.18-μm CMOS Technology

This paper presents a low-dropout voltage regulator (LDO) with a slew-rate enhancement circuit. The proposed slew-rate enhancement circuit was utilized to generate a large current for driving a large pass transistor and quicker charge and discharge of the parasitic capacitance. Hence, the transient response of the LDO was significantly enhanced owing to the improvement in the slew rate at the gate of the pass transistor. The proposed LDO regulator was designed and fabricated using the SMIC 0.18-[Formula: see text]m standard CMOS process, and its core area occupation was only 0.012[Formula: see text]mm 2 . The measurement results show that the output overshoot/undershoot voltages and settling times of the proposed LDO with SRE are 190[Formula: see text]mV/267[Formula: see text]ns and 174[Formula: see text]mV/233[Formula: see text]ns when the load current changes between 100[Formula: see text][Formula: see text]A and 100[Formula: see text]mA. It has a moderate figure-of-merit (FOM) of 0.267[Formula: see text]ns.