Most semiconductor manufacturers expect 193nm immersion lithography to remain the dominant patterning technology through the 32nm technology node. If this remains the case, the interaction of more complex designs with shrinking process windows will severely limiting parametric yield. The industry is responding with strategies based upon design for manufacturability (DFM) and multi-variate advanced process control (APC). The primary goal of DFM is to enlarge the process yield window, while the primary goal of APC is to keep the manufacturing process in that yield window. In this work, we discuss new and innovative process metrics, including simulation-based virtual metrology, that will be needed for yield at the 32nm technology node.