A 3D-WLCSP package technology: Processing and reliability characterization

A new low cost 3 Dimensional Wafer Level Chip Scale Package (3D-WLCSP) technology that leverages the existing infrastructures of wafer level packaging and high volume flip chip assembly is presented. This paper provides an overview of the new 3D-WLCSP technology including Flip Chip on wafer bonding assembly technologies required to produce the 3D Face to Face Flip Chip on wafer package. Development efforts are focused on high density flip chip placement forming the 3D-WLCSP and the associated innovations that this type of packaging and assembly includes. In this work, the flip chip pitch and bump size is varied as well as key assembly materials (including fluxes and underfills) used to attach the flip chip to the WLCSP. Processing innovations developed include flip chip fluxing methods for very fine pitch and small bump sizes, vision recognition of the chip and substrate during assembly, reflowing of the flip chips on a wafer, and underfilling a solder balled WLCSP wafer with chip components in close proximity. Initial reliability results are presented which highlight that even though the flip chip is mounted silicon to silicon, the pitch and bump size make it so that the underfill selection has a large impact on the reliability of the assembly. Various aspects of the die to wafer assembly process are explored including scaling issues with high volume assembly, utilization of low cost underfill approaches such as no flow underfills and wafer applied underfills, and underfill encroachment on the WLCSP balls. Flux and underfill material combinations are identified that enable high assembly yields and provide reliable 3D-WLCSP assemblies with respect to liquid to liquid thermal shock testing and unbiased autoclave aging.