Hybrid Source Laterally Diffused MOS Drain Engineering for ESD Robustness

The Hybrid source laterally diffused MOS (LDMOS) eliminates snapback of the LDMOS due to the parasitic bipolar junction transistor (BJT). The safe operating area (SOA) and power to failure are no longer limited by the parasitic BJT, but rather by the drain engineering of the device. The impact of drain engineering schemes on these metrics can be explored in the absence of BJT induced snapback. Under grounded gate, very fast transmission line pulse (vf-TLP) conditions, adopting an optimized stepped shallow trench isolation (STI) drain architecture increased the Hybrid source LDMOS power to failure by 68% without compromising the size of the device.