Interface engineering for substantial performance enhancement in epitaxial all-perovskite oxide capacitors

Abstract Capacitors based on ABO 3 -type perovskite oxides show considerable promise for overcoming the limitations of nanoscale integration with dynamic random access memory (DRAM) devices. Among the thermodynamically stable perovskite oxides, titanates (ATiO 3 ) exhibit high dielectric permittivity in metal–insulator–metal (MIM) configurations. However, their performance in mitigating the large leakage current caused by their narrow bandgap (3 eV) remain under scrutiny. Herein, substantially enhanced dielectric properties of an epitaxial SrRuO 3 /Ba 0.5 Sr 0.5 TiO 3 /SrRuO 3 MIM capacitor with a thin dielectric layer (10 nm) are reported. The dielectric/electrode heterointerface was engineered to realize a capacitor with a low leakage current and high dielectric permittivity. A pit-free and stoichiometric SrRuO 3 bottom electrode with an atomically smooth surface was exploited to suppress defect formation at the heterointerface. The critical roles of oxygen vacancies and substituted transition-metal atoms in determining the leakage current were assessed, and a strategy for reducing the leakage current via interface engineering was established. Consequently, a dielectric permittivity of 861 and a leakage current density of 5.15 × 10 −6 A/cm 2 at 1 V were obtained with the thinnest dielectric layer ever reported. Our work paves the way for the development of perovskite-oxide-based capacitors in next-generation DRAM memories.