Modeling and hardware implementation of universal interface-based floating fractional-order mem-elements

Fractional-order systems generalize classical differential systems and have empirically shown to achieve fine-grain modeling of the temporal dynamics and frequency responses of certain real-world phenomena. Although the study of integer-order memory element (mem-element) emulators has persisted for several years, the study of fractional-order mem-elements has received little attention. To promote the study of the characteristics and applications of mem-element systems in fractional calculus and memory systems, a novel universal fractional-order mem-elements interface for constructing three types of floating fractional-order mem-element emulators is proposed in this paper. With the same circuit topology, floating fractional-order memristor, fractional-order memcapacitor, and fractional-order meminductor emulators can be implemented by simply combining the impedances of different passive elements. PSPICE circuit simulation and printed circuit board hardware experiments validate the dynamical behaviors and effectiveness of our proposed emulators. In addition, the dynamic relationship between fractional-order parameters and values of fractional-order impedance is explored in MATLAB simulation. The proposed fractional-order mem-element emulators built based on the universal interface are constructed with a small number of active and passive elements, which not only reduces the cost but also promotes the development of fractional-order mem-element emulators and application research for the future.