Low On-State Voltage and EMI Noise 4H-SiC IGBT With Self-Biased Split-Gate pMOS

A 15-kV-scale 4H-SiC insulated-gate bipolar transistor (IGBT) with a self-biased split-gate pMOS (SGPMOS) is proposed and simulated in this work. By introducing the SGPMOS, the proposed IGBT forms a hole barrier in the ON-state and a hole extraction path during the turn-on and turn-off transient, respectively. Compared to GS IGBT, the ON-state voltage ( ${V}_{\text {ON}}{)}$ of the SGPMOS IGBT is decreased by 54.95% for the same turn-off loss ( ${E}_{\text {off}}$ ). Meanwhile, compared with pMOS IGBT, the ${C}$ – ${V}$ and gate charge ( ${Q}_{g}{)}$ characteristics exhibit that the Miller capacitance ( ${C}_{\text {gc}}{)}$ and ${Q}_{g}$ of the SGPMOS IGBT are reduced by 56.60% and 35.85%, respectively. Moreover, SGPMOS can extract the hole accumulated both under the gate oxide and in the P-shield region during the turn-on transient. This diminishes reverse displacement current ( ${I}_{G\_{}{\text {dis}}}{)}$ , contributing to low electromagnetic interference (EMI) noise. Simulation results demonstrate that, compared to pMOS IGBT, the SGPMOS IGBT achieves better controllability in peak turn-on current ( ${I}_{\text {max}}{)}$ and turn-on $\text{d}{I}_{C}/\text{d}{t}$ , featuring a 52.75% lower maximum reverse recovery $\text{d}{V}_{\text {KA}}/\text{d}{t}$ for the same turn-on loss ( ${E}_{\text {on}}{)}$ .