Impacts of HLS Optimizations on Side-Channel Leakage for AES Circuits

Many IoT devices have been compromised by side-channel attacks. Among them, power analysis attack is a well-known technique to reveal the secret key of a circuit by measuring the power of the target device. In this study, we investigate the relationship between the performance and the side-channel attack resistance of cryptographic circuits. We synthesize AES circuits from a behavioral description written in the C language and analyze the power. In order to evaluate tolerance to side-channel attacks, we conduct T-test for the power consumed on the circuit. Experimental results show that there appears a trade-off between the side-channel leakage and the performance of the circuit.