A MIS-HEMT with PIN junction gate for enhanced threshold voltage and reduced gate leakage

Abstract This work proposes a metal-insulator-semiconductor high-electron-mobility transistor with p-type i-type n-type (PIN) junction gate (MP-HEMT) to address the limitations of p-GaN AlGaN/GaN HEMTs, where achieving high threshold voltage and low gate leakage. The simulation results demonstrate that the MP-HEMTs, featuring an extended PIN junction depletion region and an insulator layer, exhibiting a significant improvement in threshold voltage (from 1.1 V to 2.3 V) while concurrently reducing gate leakage current by two orders of magnitude (from 10 −2 to 10 −4 mA mm −1 at V GS = 5 V), and the gate forward breakdown voltage is increased from 9.9 V to 16.9 V. The structure also exhibits quasi-self-alignment properties, ensuring robust gate control irrespective of gate metal alignment. Furthermore, optimizing the insulator layer reveals that a thinner thickness coupled of a higher dielectric constant achieves an optimal trade-off between gate leakage suppression and control capability. This study presents a promising approach for developing high-performance, high-power GaN-based transistors with improved threshold voltage stability and reduced gate leakage current.