A Low-Power Bayesian Head Using SOT-MRAM Arrays for Uncertainty-Aware Binary Neural Networks

This work presents a novel low-power, mixed-signal computing in memory (CIM) architecture for Bayesian inspired inference, targeting edge AI applications requiring energy-efficient uncertainty estimation. Our system integrates a deterministic Binary Neural Network (BNN) with a Bayesian head module implemented using multi-pillar (MP) Spin-Orbit Torque Magnetic RAM (SOT-MRAM) based arrays. The Bayesian head perturbs the output popcount of the BNN by injecting configurable stochastic counts, enabling uncertainty quantification in classification tasks. These perturbations are configurable in ‘flavor’ through a tunable dropout rate and the number of MP cells. A VCO-based ADC converts analog resistive summations into digital counts, which are then combined with the deterministic BNN output. On MNIST and CIFAR-10, the proposed system achieves classification accuracy comparable to state-of-the-art Bayesian approaches while consuming only 19 µW. It achieves a favorable energy efficiency of 53 TOPs/W (18.9 fJ/OPS) for 3-bits and 110 TOPs/W for 2-bits perturbation precision. Uncertainty estimation is validated through controlled domain shifts (e.g., tilted images), showing robust entropy and variance evolution. Notably, the proposed uncertainty estimation requires only 25 perturbation runs, resulting in a total energy cost of just 454 fJ. At this overhead, the Bayesian-inspired model improves reliability by 34.29% compared to the baseline on CIFAR-10. This low-power hybrid analog-digital architecture offers a promising solution for edge applications with embedded confidence metrics.