Flexible NTT Accelerator Design Framework for Scalable Lattice-Based Cryptosystems

The Number Theoretic Transform (NTT) is a widely adopted technique for accelerating polynomial multiplication in lattice-based cryptographic (LBC) systems, and it often constitutes the primary computational bottleneck. Area-time product (ATP) and scalability are two critical metrics for evaluating accelerator designs. Different cryptographic backgrounds have different security parameters, and the diverse application platforms lead to different cost-performance tradeoffs and hardware constraints. We propose a flexible NTT accelerator design framework for LBC to meet the demand for performance and scalability, supporting various polynomial degrees, moduli, radices, and parallelism. Our hardware implementations show excellent ATP efficiency, with our interconnect achieving up to $6.7 \times$ better LUT-ATP than other in-place designs under the same configuration. In-place computation demands complex memory access patterns, making the design for varying radices and parallelism tough. We propose an efficient, conflict-free memory mapping scheme that offers scalability for different configurations. Compared to other in-place architectures, our approach significantly reduces interconnect complexity. On average, the accelerators generated by our proposed framework are 65.1% more area-time efficient. Up to 34.9% area-time reduction over the state-of-the-art scalable NTT accelerator can be achieved for the same security parameters.