Metal oxide resist (MOR) EUV lithography processes for DRAM application

This paper reports the readiness of key EUV resist process technologies using Metal Oxide Resist (MOR) aiming for the DRAM application. For MOR, metal contamination reduction and CD uniformity (CDU) are the key performance requirements expected concerning post exposure bake (PEB). Based on years of experience with spin-on type Inpria MOR, we have designed a new PEB oven to achieve contamination mitigation, while keeping our high standard of CDU. The new bake oven was introduced in our coater and developer and evaluated using line/space patterns. As described in the results, exceptional CD uniformity was realized while exceeding the metal contamination specification. The new plate design also enabled a 30% reduction in dose-to-size without degradation of CDU when applying higher PEB temperature. Another challenge for the DRAM application in particular is pattern collapse as applied to pillar patterns. By optimization of several parameters, the pattern collapse margin extended the minimum CD by 13.8%. The result was achieved with a combination of SiC in place of SOG for under layer, thinner resist film thickness and a modified resist material, MOR-B. Finally, to achieve target yield performance, defectivity reduction is also an important task towards MOR application. An integrated approach is needed to realize scum free patterning because if metal residuals remain in the open space, they can cause yield-killing defects. By analyzing possible root causes of defect sources, we attempt to eliminate etch-masking scum layer present after conventional developer processing. By applying a post develop rinse including novel hardware for defect reduction, bridge defects were reduced up to 19% with new the technology.