Tunable Linearity of Weight Update in Low Voltage Synaptic Transistors with Periodic High‐k Laminates

Abstract Synaptic transistors have shown great potential in neuromorphic computing, but remain challenging to simulate linear weight updates through conductance switching under low voltage spiking operation. Here, a low voltage and near‐linear weight update synaptic transistor are proposed by developing an interfacial‐defect dominated floating gate structure, in which inter‐diffused defects are surrounded by near‐defect free and ultrathin (1 nm) dielectrics in HfO 2 /Al 2 O 3 periodic high‐ k laminates. In the laminates, inter‐diffused defects are surrounded by near‐defect free and ultrathin (1 nm) HfO 2 and Al 2 O 3 tunneling layers deposited by atom layer deposition, which contributes to the accurate regulation of multi‐level charge trapping confined at independent interfacial regions, and trades off the low operation voltages and the nonvolatile characteristics of the devices. A very small conductance switching nonlinearity (NL = 0.05) and an excellent image recognition accuracy (93.1%) are demonstrated under low voltages (−3 V/1.8 V) in an optimized device with (1 nm HfO 2 /1 nm Al 2 O 3 ) 3 laminates. Besides, the basic synaptic functions are successfully mimicked based on the long‐term plasticity. These results have referential significance for the future artificial synapse with low energy consumption and high efficiency.